[SOLVED] Verilog Problem - Large Bus Bit Checking

[forkconfig]

Using Verilog...

Let's say I have a 1000 bit bus.
I want to check that the MSB (2^1000) is high and everything else is low (or any bit for that matter).
I don't want to sit there and go 1000000000000000000... or 0x8000000000000000000...

If it was the LSB I could just say if bus == 1, but I don't want to say if bus == 2^1000 because that's sort of a big number.

Is there a way to use a wild card or something in Verilog?

 

[dave_59]

the best thing to do in this case is use bit selects

(bus[BUS_WIDTH-1] & bus[BUS_WIDTH-2:0] == 0) // all bits low
(bus[BUS_WIDTH-1] & (&bus[BUS_WIDTH-2:0]) == 0) // any bits low

 

[forkconfig]

Ohh that's a good idea. But I am not too sure what the code you wrote is doing
(bus[BUS_WIDTH-1] & bus[BUS_WIDTH-2:0] == 0) // all bits low
(bus[BUS_WIDTH-1] & (&bus[BUS_WIDTH-2:0]) == 0) // any bits low

In line 1 it seems like you are setting all the bits to the value of bus[BUS_WIDTH-1] (asumed to be 0) but then your saying "== 0", how come?
Also in line 2, I am not sure what that second & sign inside the brackets does.

Based on what you said let me see if I got this...

To check if bit x is high and all others are low:
if ( (bus[BUS_WIDTH-x-1:0] == 0) && (bus[BUS_WIDTH-1:bus[BUS_WIDTH-x+1] == 0) && (bus[x] == 1) )

To set all bits to 0 and the x'th bit to 1:
bus[BUS_WIDTH-x-1:0] <= 0
bus[BUS_WIDTH-1:bus[BUS_WIDTH-x+1] <= 0
bus[x] <= 1

Please tell me if what I did is poor coding practice, I'm open to criticism.
Thanks

 

[dave_59]

You originally said you wanted to check the bus, not set it, so I showed you an expression you could check; in an if statement perhaps.

Actually, I made a mistake. I should have wrote

(bus[BUS_WIDTH-1] && bus[BUS_WIDTH-2:0] == 0) // all bits low

The difference is '&&' is logical AND versus '&' is bitwise AND.

The '&bus' in line 2 is the reduction AND operator - that ANDs every bit int the bus together so that they all must be 1 to produce a 1.

In Verilog, x must be a parameter, not a variable. There can be no variable width expressions.

You could use a temporary bus variable:

// check if bit x is high and all others are low
bus_temp = bus;
bus_temp[x] = 0;
if (bus[x] && bus_temp == 0) ...

// set all bits to 0 and the x'th bit to 1:
bus <= 0;
bus[x] <= 1; // this works because last write wins.

 

[forkconfig]

I was using x more as pseudo code style.
But thanks for all your help

One last question, I don't quite understand the reduction operator:

(bus[BUS_WIDTH-1] & (&bus[BUS_WIDTH-2:0]) == 0) // any bits low

What do you mean every bit is ANDED with each other?

If it helps let's simplify this...
input [5:0] bus;

always @(posedge clk) begin
bus <= &bus;
end

What would that do?
Did I use it right?

 

[dave_59]

Reduction operators return a single bit. Look at Section 11.4.9 Reduction operators in the LRM. Don't have a copy, get one here.