davidgrm
Full Member level 4
Hi - I get the following errors listed below If the commented out lines in module 2 are enabled the errors go away but then the logic is not what I require any suggestions would be welcome
error:
Warning: Latch IO_Select:IO_Select_1|CS_1_Page_1 has unsafe behavior
Warning: Ports D and ENA on the latch are fed by the same signal IO_Select:IO_Select_1|BankReg[0]
Warning: Latch IO_Select:IO_Select_1|CS_0_Page_1 has unsafe behavior
Warning: Ports D and ENA on the latch are fed by the same signal IO_Select:IO_Select_1|BankReg[0]
//////module1
always@(Write or Command)
begin
if(Command && Write)
begin
Cmd_Reg[3:0] <= PC_Dat[7:4];
Bnk_Reg[3:0] <= PC_Dat[3:0];
end
end
//////module 2 - Bnk_Reg[3:0] is connected between module 1 and 2
// {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
input [3:0] Bnk_Reg;
input Read;
input Write;
output CS_0;
output CS_1;
output CS_0_Page_1;
output CS_1_Page_1;
// {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
reg [3:0] BankReg;
reg CS_0;
reg CS_1;
reg CS_0_Page_1;
reg CS_1_Page_1;
//
parameter Ext0_Ram = 4'b0001,Ext1_Ram = 4'b0010,Prog_Ram = 4'b0011;
parameter Data_Ram = 4'b0100;
//
always @(posedge Write)
begin
BankReg[3:0] = Bnk_Reg[3:0];
end
always @(BankReg[3:0])
begin
case(BankReg[3:0])
Ext0_Ram:
begin
CS_0 = 1'b0;
CS_1 = 1'b1;
CS_0_Page_1 = 1'b0;
//CS_1_Page_1 <= 1'b0;
end
Ext1_Ram:
begin
CS_0 = 1'b0;
CS_1 = 1'b1;
CS_0_Page_1 = 1'b1;
//CS_1_Page_1 <= 1'b1;
end
Prog_Ram:
begin
CS_0 = 1'b1;
CS_1 = 1'b0;
CS_1_Page_1 = 1'b0;
//CS_0_Page_1 <= 1'b1;
end
Data_Ram:
begin
CS_0 = 1'b1;
CS_1 = 1'b0;
CS_1_Page_1 = 1'b1;
//CS_0_Page_1 <= 1'b1;
end
default:
begin
CS_0 = 1'b1;
CS_1 = 1'b1;
end
endcase
end
error:
Warning: Latch IO_Select:IO_Select_1|CS_1_Page_1 has unsafe behavior
Warning: Ports D and ENA on the latch are fed by the same signal IO_Select:IO_Select_1|BankReg[0]
Warning: Latch IO_Select:IO_Select_1|CS_0_Page_1 has unsafe behavior
Warning: Ports D and ENA on the latch are fed by the same signal IO_Select:IO_Select_1|BankReg[0]
//////module1
always@(Write or Command)
begin
if(Command && Write)
begin
Cmd_Reg[3:0] <= PC_Dat[7:4];
Bnk_Reg[3:0] <= PC_Dat[3:0];
end
end
//////module 2 - Bnk_Reg[3:0] is connected between module 1 and 2
// {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
input [3:0] Bnk_Reg;
input Read;
input Write;
output CS_0;
output CS_1;
output CS_0_Page_1;
output CS_1_Page_1;
// {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
reg [3:0] BankReg;
reg CS_0;
reg CS_1;
reg CS_0_Page_1;
reg CS_1_Page_1;
//
parameter Ext0_Ram = 4'b0001,Ext1_Ram = 4'b0010,Prog_Ram = 4'b0011;
parameter Data_Ram = 4'b0100;
//
always @(posedge Write)
begin
BankReg[3:0] = Bnk_Reg[3:0];
end
always @(BankReg[3:0])
begin
case(BankReg[3:0])
Ext0_Ram:
begin
CS_0 = 1'b0;
CS_1 = 1'b1;
CS_0_Page_1 = 1'b0;
//CS_1_Page_1 <= 1'b0;
end
Ext1_Ram:
begin
CS_0 = 1'b0;
CS_1 = 1'b1;
CS_0_Page_1 = 1'b1;
//CS_1_Page_1 <= 1'b1;
end
Prog_Ram:
begin
CS_0 = 1'b1;
CS_1 = 1'b0;
CS_1_Page_1 = 1'b0;
//CS_0_Page_1 <= 1'b1;
end
Data_Ram:
begin
CS_0 = 1'b1;
CS_1 = 1'b0;
CS_1_Page_1 = 1'b1;
//CS_0_Page_1 <= 1'b1;
end
default:
begin
CS_0 = 1'b1;
CS_1 = 1'b1;
end
endcase
end