[SOLVED] [Verilog] Output problem

[Crabe05]

Hi everybody.
I've made 2 'memory8' module (that store 8 bits encoded data). One is read-only, the other is read-write. Here is the output with the ro memory :

[00]: 10100010 (a2|162)
[3f]: 01100101 (65|101)
[6d]: 00011011 (1b| 27)
[ff]: 10000111 (87|135)
[a2]: 00000000 (00|  0)
[3f]: 01100101 (65|101)

All is good.
But with rw memory :

read
[00]: 10100010 (a2|162)
[3f]: 01100101 (65|101)
[6d]: 00011011 (1b| 27)
[ff]: 10000111 (87|135)
write
[a2]: xxxxxxxx (xx|  x)
[a2]: 10011001 (99|153)
[3f]: 00001111 (0f| 15)
read
[3f]: 0xx0x1x1 (XX|  X)
[a2]: 00000000 (00|  0)
[3f]: 0xx0x1x1 (XX|  X)

Ouch !!

What happened ?
Thanks a lot, Crabe.

 

[nafraf]

I think that people will need to see your code to help you.