Verilog Netlist generation

[sandysuhy]

Hi All,
I have inserted power switches(Header/Footer) , Isolation cells and state retention cells in an ASIC design using Common Power format (CPF) . I have completed till floorplan , but after that if I am generating netlist I am not able to get Header/Footer in the netlist .
I am using Cadence encounter 6.2 and i have a tapeout in near future.
hence can anyone help me.

Regards
Sandeep.

 

[itsmeteja]

I do not have prior experience working with the encounter tool.But the concept remains the same, you need to specify the list of cells to be included as the option in the write netlist command.