[SOLVED] Verilog: Need help with 8bits accumulator using 4bits adder.

[u24c02]

Hi.
I need to construct an 8-bit accumulator. For this, I need an 8-bit adder.
But my ASIC vendor’s technology library has only 4-bit adders. So I construct
the accumulator.
When I synthesized the circuit, I found that there was a max-delay violation on the “Carry” signal between the two adders. To correct this, I added a flip flop in the Carry-path, as follows.



But the problem is that the output result wrong. But I don't know. what changes need to be made to this new circuit?

Please help me

 

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When I synthesized the circuit, I found that there was a max-delay violation on the “Carry” signal between the two adders. To correct this, I added a flip flop in the Carry-path, as follows. But the problem is that the output result wrong. But I don't know. what changes need to be made to this new circuit?

How did you expect adding a register to a combinatorial path would still let the carry work? I think you better go back and look at the design of an adder, follow the carry path and see for yourself that adding a register to that path breaks the adder.

Either create a pipelined adder (which is not the same as daisy-chaining adders), make a carry look ahead adder, or start researching designs for other fast carry adders.

I'm really surprised that in an ASIC an 8-bit adder doesn't make timing, what clock frequency is that adder running at?

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If you can live with a pipelined adder and have to use the 4-bit library adder.


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Okay I fixed the missing carry pipeline register (the register you added) and moved the blocks around so it's easier to see the "pipelined" architecture using the 2 nibble adders. I'm assuming the nibble adders are combinational.

 

[u24c02]

Thanks great! sir, I have some question
first, is pipe upper nibble means just flip-flop register? Or something else?

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Thanks great! sir, I have some question
first, is pipe upper nibble means just flip-flop register? Or something else?

I have totally got it.Thanks Sir again.