Verilog - Multiple Calls to Task

[forkconfig]

Let's say there is a task called myTask() that looks something like this:

task myTask;
input a;
input b;

begin
/* STUFF */
end
endtask

Let's say in my module I have two sections of code calling this task

module (
varQ
varW
varE
varR
);

// call this section of code Alpha
always @(...) begin
myTask(varQ, varW);
...
end

// call this section of code Beta
always @(...) begin
myTask(varE, varR);
...
end

Okay now here is my question...
If Alpha calls myTask first, then while it is still running Beta calls myTask, it is my understanding that the variables will be overwritten. Therefore, whatever Alpha calculates will be based off the overwritten values of Beta. How can I avoid this conflict?

Thanks

 

[TrickyDicky]

all the vars in your code are individual so there is no conflict. the two calls are completly independent.

 

[dave_59]

If myTask does not any consume time, there is not much of a problem because one call will finish before the next call starts. ( and you should be using functions, not tasks if they are not supposed to consume time). But technically threads are allowed to interleave, sou you can declare your task/function as automatic. Then each call gets its own set of variables.

 

[ads_ee]

You probably want to use.

task automatic myTask;

Using the automatic keyword makes the task re-entrant. Which is what you might want if your task can be called in two sections of code simultaneously. This is something introduced in Verilog 2001.