Verilog Module inside a TCL file

[Harishddixit]

Hi ...I am trying to parameterize a module...say a module which has one of the values which needs to be controlled via the TCL testcase.
So how to do it ??
I know how to call Verilog Tasks but I dont know how to call Verilog Module

Thank You

 

[osm3000]

To make it easy, you can group the parameters you want in a single file.
In the TCL script, after you make your calculations for the parameters, make the script output the new parameters to this file of parameters,
then start compiling your design.