verilog mod3 counter query on assign statements

[strangesiva]

Hi ,
the below code uses dff for mod3 counter design . rst generated (using expression1) does not work,where as rst generated (using expression 2) works . what is the reason ?

---

Code Verilog - [expand]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
module dff(output reg q,output qn,input d,clk,reset);
always @(posedge clk or negedge reset)
begin
if(!reset)
q<=1'b0;
else
q<=d;
end
assign qn=~q;
endmodule
module mod3(output clk_3,input clk,reset);
wire q0,q1,qn0,qn1,rst,temp;
dff dff0(q0,qn0,qn0,clk,rst);
dff dff1(q1,qn1,qn1,qn0,rst);
assign clk_3=q1;
//assign rst=reset & ~(q0 & q1); //this expression1 does not work 
assign rst=reset & temp; //this expression2 works 
assign temp=~(q0 & q1);
endmodule

---

 

[ads-ee]

Both are valid assign statements.

So how about telling us how it doesn't work instead of just telling us it doesn't work.

One observation though. This circuit might not work in hardware, if the rst output has glitches due to the differences in delay from skewed generated clock qn0.

 

[strangesiva]

Both are valid assign statements.

So how about telling us how it doesn't work instead of just telling us it doesn't work.

One observation though. This circuit might not work in hardware, if the rst output has glitches due to the differences in delay from skewed generated clock qn0.

I was simulating the above code in xilinx ise and modelsim . I wanted to know how it happens so i posted this thread .
Ok if you mention about the skew factor , in reality how are the reset signals to mod counters realised ?

Thanks

 

[ads-ee]

The code is easy to break...

---

Code Verilog - [expand]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
`timescale 1ns/1ns
 
module dff (
  output reg q,
  output qn,
  input d,clk,reset
);
 
always @(posedge clk or negedge reset) begin
  if(!reset)
    q<=1'b0;
  else
    q<=d;
  end
 
assign qn=~q;
 
endmodule
 
module mod3(
  output clk_3,
  input clk,reset
);
 
  wire q0,q1,qn0,qn1,rst,rst2,temp;
  wire q0_dly, q1_dly;
 
  dff dff0(q0,qn0,qn0,clk,rst);
  dff dff1(q1,qn1,qn1,qn0,rst);
 
  assign #2 q0_dly = q0;
  assign #1 q1_dly = q1;
 
  assign clk_3=q1_dly;
  assign rst2=reset & ~(q0_dly & q1_dly); //this expression1 does not work 
  assign rst=reset & temp; //this expression2 works 
  assign temp=~(q0_dly & q1_dly);
 
endmodule
 
module tb_mod3;
 
  reg clk, reset;
  wire clk_div3;
 
  initial begin
    clk = 0;
    forever #10 clk = ~clk;
  end
 
  initial begin
    reset = 0;
    #150;
    reset = 1;
  end
 
  mod3 uut (
    .clk_3  (clk_div3),
    .clk    (clk),
    .reset  (reset)
  );
endmodule

---

As you can see I added different delays for q1 and q0, emulating differences in routing delay to the LUT that generates the ~(q1 & q0) term.

Here is the simulation output:


This is what I meant by glitches on the reset, as you can see the reset pulse is one time unit of the simulation. To make this circuit work across temperature and process would require delay matching between the q0, q1, qn0, and qn1 outputs or purposely skewing the delays for q1 and qn1 to always arrive later than q0 and qn0. I've seen other mod3 circuits that don't have this kind of behavior, they typically use opposite edge clocking and some signals to indicate the clock phase of the source clock you are in to generate the toggles.

Regards

- - - Updated - - -

Here is one example of a divide by 3 that doesn't exhibit glitches due to small variations in placement and routing (see page 5)
https://www.mikrocontroller.net/attachment/177198/Clock_Dividers_Made_Easy.pdf