Shahzad40
Newbie level 5
lec verilog
Hi,
look at the following code:
input TX_IN;
reg [12:0] Rx;
always @ (posedge CLK)
begin
if(CLR)
....
....
Rx <= ~TX_IN;
..
else
...
end
Can anyone tell me with authority will the Rx[0] will get the inverted of TX_IN or all the bits of Rx will get inverted of TX_IN ?
The reason i am asking is cause i thought only the LSB gets inverted so i changed the code to
Rx [12:1] = 12'b0;
Rx[0] = ~TX_IN;
and when I LEC the two code, the LEC reported that the two codes are unequivalent
Regards,
Hi,
look at the following code:
input TX_IN;
reg [12:0] Rx;
always @ (posedge CLK)
begin
if(CLR)
....
....
Rx <= ~TX_IN;
..
else
...
end
Can anyone tell me with authority will the Rx[0] will get the inverted of TX_IN or all the bits of Rx will get inverted of TX_IN ?
The reason i am asking is cause i thought only the LSB gets inverted so i changed the code to
Rx [12:1] = 12'b0;
Rx[0] = ~TX_IN;
and when I LEC the two code, the LEC reported that the two codes are unequivalent
Regards,