Melinda123
Newbie level 1
Hi,
I have a (maybe silly) question :
Suppose we have few counters in FPGA design... used to index some particular registers, memories etc...
Explanation:
Suppose we need to index zero element from some register...if we start to count after reset i.e. (suppose 5 bit counter) cnt <= cnt + 1; we have on first posedge of clk signal, that cnt value is 1 but we needed 0.
So we need to set cnt <= 5'b11111; when reset occur, and then after reset on first posedge of clk signal we would have cnt is 0 as we needed.
Is it good practice, when we need to reset those counters that we reset their (all) bits to 1 and not 0 as usually people do. Does it matter (power consumption or ...)? Can someone clarify.
Best regards
I have a (maybe silly) question :
Suppose we have few counters in FPGA design... used to index some particular registers, memories etc...
Explanation:
Suppose we need to index zero element from some register...if we start to count after reset i.e. (suppose 5 bit counter) cnt <= cnt + 1; we have on first posedge of clk signal, that cnt value is 1 but we needed 0.
So we need to set cnt <= 5'b11111; when reset occur, and then after reset on first posedge of clk signal we would have cnt is 0 as we needed.
Is it good practice, when we need to reset those counters that we reset their (all) bits to 1 and not 0 as usually people do. Does it matter (power consumption or ...)? Can someone clarify.
Best regards