[9:0] is 10 bits wide, i.e. 9,8,7,6,5,4,3,2,1,0 which is 10 digits.
[8:0] is 9 bits wide
a*b is 19 bits wide not 17 (9+8)
a*b +1'b1 will be 19 bits wide not 20, a*b will never be all 1's so adding a 1'b1 will never increase the result's bit width.
a*b +3 will fit in 19 bits but the result is 32-bits due to the 3 which is an integer (dependent on implementation, but is normally 32-bit)
I've been using Verilog for ~20 years, so I've probably seen + used with practically every possible thing.
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The integer math is the most annoying as it causes additional warnings in synthesis when it sees a 32-bit result being assigned to a smaller bit width variable. As long as you're willing to ignore those (I usually do) and can get through any reviews with those warnings in your synthesis report they aren't a problem.