[verilog] `include with path, relative to user home directory

[bene_]

Hello,

I'm relatively new to Verilog and have a question about the `include directive.
Is it somehow possible to use ~/ in the path? It was not possible for me to make it work. I need to use the ~ and cannot use /home/<username>/ because it should work on different user accounts with local files.

 

[jt_eaton]

The traditional method was to use only the filename and let the toolflow set the searchpath to find it. This worked fine until about 10 years ago when design size and complexity became overwhelming. Calling your defines file "defines.v" works great until two or three other designers on your chip do the same thing.

Today the best solution is for the toolflow to run each individual component thru a verilog preprocessor before loading them into the SOC. Your search path is tiny and you never have to worry about namespace collisions in the `tic namespace.