[SOLVED] Verilog: In which case use "Wire" and in which case "Register"

[sheikh1]

Hello Everybody,

I am trying to learn Verilog.
While going through some Verilog code in books and internet, I found difficulties to understand In which case I have to use Wire and in which case Register.

What I have understood that when we have to store/Pass signal in the design, then use "Register" otherwise "Wire" but still quite confusing like input or output or inout case.

Is the Wire analogous to Variable in VHDL and Register analogous to Signal in VHDL?

Can anybody please clarify me? with an example would be more better.
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Regards
Sheikh

 

[DFT_designer]

Re: Verilog: In which case use "Wire" and in which case "Register"

Hello,

Here is an attempt to answer your question from my personal experience:
An input is not declared as reg or wire.
An output is declared by default as wire.
If an output receive a value, then it must be declared as a reg.
Reg and wires are used in the design not only for outputs but also as intermediate signals.
It is difficult to make the analogy with VHDL. But if we have to make it, I would like to say that reg and wires will be declared both as "signal".
The difference is that a wire is a connection (signal used in mapping in VHDL) and reg is a signal used to store a value.
That is not a full answer for sure, it is just a small attempt to answer
You can find an example in this link: https://www.asic-world.com/tidbits/wire_reg.html
Best Regards

 

[beeflobill]

Re: Verilog: In which case use "Wire" and in which case "Register"

I believe this is a common problem for newcomers to Verilog.

Essentially, the wire datatype is to remind us of real wires in electronic circuits. Likewise, the reg datatype is supposed to remind us of registers in electronic circuits.

To contrast wires and regs:

wire:
Wires must be driven to a value, they do not store data.
Wire behavior is not defined in procedural code
Wire values are updated continuously (every timestep)
Wires provide connectivity between devices, like real wires in electronic circuits. So, the outputs and inputs of an AND gate will be a wire.
Wire values can be accessed at any time. So, if A and B are wires: assign A = B;

reg:
Registers store data. They can not be driven
Register behavior is defined in procedural code
Register values are updated at specific events, like the positive edge of a clock. Like: always @ (posedge CLK) begin ... end
Registers provide data storage, not connectivity.
Register values can be accessed at any time. So, if A is a wire and B is a register: assign A = B;

I'd like to make a small clarification/correction to DFT_designer. "An input is not declared as reg or wire." This could easily be read as "inputs do not have a wire or reg datatype" which is false. But what I think what was intended is, "inputs are wires and the user can not change it" which is true. This goes along with his next statement, which is that outputs can either be wires or regs.

I hope that this is helpful. I'm not very familiar with VHDL, so I can't draw a comparison. Although, the best general advice I can offer for trying to decide when to use this or that in Verilog is to try to design and understand the circuit you are trying to realize before you start to write code. If you have a block diagram scribbled onto a piece of paper in front of you, then it should be very clear from it what is a register and what is a wire.

 

[DFT_designer]

Re: Verilog: In which case use "Wire" and in which case "Register"

Yes I agree about inputs, they cannot be changed, I have badly expressed myself.
I agree also with your last comment: a good designer should start with a paper and a pencil, and after that describe it with a description language.

Thanks and Regards,

 

[dave_59]

Re: Verilog: In which case use "Wire" and in which case "Register"

I have a blog post on that: https://go.mentor.com/wire-vs-reg

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I have a blog post on that: http://go.mentor.com/wire-vs-reg