Verilog in Analog designing plus Verilog in Digital Designin

I have done Verilog designing concept in digital aspect ,now i am moving to shift in analog designing in verilog in below describe coding I have tried to design Conductive Resistace in verilog programming there are three query regard it.
1.Is simple verilog proagrmme on which I have done digital circuit coding may use same for Analog verilog programming
or 2.For analog verilog programming verilog version is different for both(i meas for Digital designing seperate verilog simulator used and for Anlog vice versa?)
3.So, if 2. is correct so may same rule apply on Model sim and ISweb software too mostly use for Spratan trainner kit
4.please check my code of simple conductive resistance ,this code is running on Verilog_AMS simulation software but not running at simple Verilog (SynCad ) Simulation software , I have a confusion plz solve this confusion which I have been facing since 3 hour........................



Is any code fault
module res2(p, n);
inout p, n;
electrical p, n;
parameter real r=1;
analog begin
V(p,n) <+ r*I(p,n);
end
endmodule

verilog is a language designing digital circuit, isn't it?