Verilog: How to use non--blocking instead of blocking statments?

[hmms]

I want to replace the blocking statements with non-blocking staements in the following code without changing the functionality of the code .

I am newbie at verilog. can someone please guide me on how to go ahead with this problem?

module q4(out ,in,clock,reset)
	output out ;
	input in,clock,reset ;
	reg out;
	reg[7:0] data;
	always @ (negedge reset of posedge clock) begin
		if (~reset) data = 8b'1111 1111;
		else begin 
			data = data << 1;
			data[0] = in;
			if(data == 8'b0111 1110) out = 1; else
				out = 0; end 
		end

Thanks a lot!

 

[dave_59]

There is no need to use a non-blocking assignment to data since it is read and written withing thew same always block.
You do want to use a non-blocking assignment to out since it may be read on the same clock edge in another module.

module q4(
    output reg out,
    input wire in,clock,reset
       );

    reg[7:0] data;
    always @ (negedge reset or posedge clock) begin
        if (~reset) data = 8b'1111_1111;
        else begin 
            data = {data[6:0], in};
            if(data == 8'b0111_1110) 
                           out <= 1; 
                        else
                          out <= 0;
        end

 

[hmms]

This question was asked to me in an interview. Was curious as to how it could be done.
Btw even i replied to the question with a code similar to what you have suggested.
what could be the another way of doing it by completely eliminating the blocking statements.

 

[FvM]

You have to use the RHS of the assignment in the comparison. That's what the blocking statement actually does.

if ({data[6:0, in} == ...