Hi, guys. I have a verilog problem.
In verilog, how do we lock the value?
What I mean is that I have a counter, and I want to increase it only one time.
If I put counter in the sequential block . It will increase when every posedge clock arrive. It's not what I desired. I want to increase the counter again until next enable signal arrive.
How can I achieve this?
For example, A is my input
Code:
always@(posedge clk)
begin
if (A)
counter <= counter + 1;
end
It will increase the counter when every psoedge clk arrive.
But I want the counter only increase once. And it increase again when A signal is change.
Please help
Can you tell the clock u use to generate the A signal?
Say, if u generate the A signal with a lesser clock than clk then counter increments many times.
What is the A signal? A 1 bit value? The way your counter is setup now it will increase on the positive edge of the clock whenever A is not equal to 0. You may need to refine your if logic.
For instance, create a register for the previous value of A and register it every clock cycle. Then increment your count when A != A_prev.