There are two ways in which pin-to-pin delays can be expressed. A path delay can be constant for all possible conditions and independent from the rest of the circuit or it can depend on various internal or input conditions. Path Delays can therefore be either non-conditional or conditional. They must always be defined within a specify block, inside a module. A description of the syntax for defining non-conditional path delays is contained in the section on the Specify Block. In summary, the paths in a module can be defined as a number of Parallel Connections, each one specified using the => symbol, or as a set called a Full Connection, in which all paths implied using the *> symbol have an equal delay. For a module with many paths, a mix of Parallel and Full connections can be used to assign the various delays.
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