Verilog hdl code 1hz

[queencythea]

hello, can someone explain to me the following codes below?i really don't understand these. please help:-(


module progdiv(clk,rst,clk1Hz);
parameter WIDTH=25; // default 25-bit counter
input clk; // 50MHz
input rst;
output clk1Hz;
reg clk1Hz;
reg [WIDTH-1:0] cnt;
always @(posedge clk, posedge rst)
begin
if (rst) begin
cnt <= 0;
clk1Hz <= 0;
end else if (cnt == 25000000) begin
cnt <= 0; // wrap around
clk1Hz <= ~clk1Hz; // toggle
end else begin
cnt <= cnt + 1;
end
end

 

[Rohitchampion]

What exactly you didn't understand in this code? Are you familiar with verilog syntax and logic?

 

[imbichie]

This is nothing but just a clock divider code.
If the input clock is 50MHz, then the output will be 1Hz,
means its a divide by 50,000,000.

But there are mistakes here
1. If you really want 1Hz, then you should give 24999999, instead of 25000000, because the counter includes the zero, or you can put the less than (< ) operator instead of equal to (==)
2. You should specify the base of the counter, means the base should be decimal. Other wise count will change, i think default it will take it as hexadecimal (i don't remember the default base), so here you can put 25'd2500000 or 25'd24999999.

 

[imbichie]

2. You should specify the base of the counter, means the base should be decimal. Other wise count will change, i think default it will take it as hexadecimal (i don't remember the default base), so here you can put 25'd2500000 or 25'd24999999.

Here i am mistaken, the default base in verilog is decimal, so if the base is not specified its treated as decimal.