VERILOG: Fixed point library

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Hi. I need to use fixed point numbers in my Verilog module and i looking for some special libraries for that. I have found one but its VHDL lib. Can you guys help me with that please.
 

Could you please explain a little bit more what kind library you need?

Tiksan,
 

I wrote program for ACTEL FPGA using Libero IDE with verilog language. I was using in this program real variables that Synplify synthesiser not compiling. I need to substitute that kind of vars with vars defined thru reg or wire types.
 

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