Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

VERILOG: Fixed point library

Status
Not open for further replies.

FPGAdevel

Newbie level 3
Joined
Nov 12, 2009
Messages
4
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,301
Hi. I need to use fixed point numbers in my Verilog module and i looking for some special libraries for that. I have found one but its VHDL lib. Can you guys help me with that please.
 

Syswip

Advanced Member level 4
Joined
Nov 11, 2009
Messages
119
Helped
12
Reputation
24
Reaction score
4
Trophy points
1,298
Activity points
1,859
Could you please explain a little bit more what kind library you need?

Tiksan,
 

FPGAdevel

Newbie level 3
Joined
Nov 12, 2009
Messages
4
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,301
I wrote program for ACTEL FPGA using Libero IDE with verilog language. I was using in this program real variables that Synplify synthesiser not compiling. I need to substitute that kind of vars with vars defined thru reg or wire types.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top