Verilog Filter design reset and enable Problem

Milruwan · Jan 31, 2014

I design a filter using Matlab hdl coder. But the problem is filter doesn't give filtered output. When I do the simulation in matlab filter works perfectly, but when I test with modelsim filter is not giving the filtered output. Problem is with the way of resetting and enabling the filter.

filter inputs and outputs

Code:

module filter
               (
                clk,
                clk_enable,
                reset,
                filter_in,
                filter_out
                );

input_reg_process

Code:

always @ (posedge clk or posedge reset)
    begin: input_reg_process
      if (reset == 1'b1) begin
        input_register <= 0;
      end
      else begin
        if (clk_enable == 1'b1) begin
          input_register <= filter_in;
        end
      end
    end // input_reg_process

Here is the output I got (reset and enable signal are also shown in the figure)

reset_my : is the reset
ce_my: is the enable

axcdd · Jan 31, 2014

can you post the whole code with testbench ? Because its hard to tell from that scratch anythink. I dont see in wave input_register, and what is zc_out ?

rajavel.rv · Feb 13, 2014

where u r using that "input_register"; and send the full code and clear waveform this module alone....

Verilog Filter design reset and enable Problem

Milruwan

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axcdd

Full Member level 3

Milruwan

rajavel.rv

Member level 3

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Verilog Filter design reset and enable Problem

Milruwan

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axcdd

Full Member level 3

rajavel.rv

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