Continue to Site

# Verilog error with for loop

Status
Not open for further replies.

#### ykishore

##### Member level 3
I am trying to synthesize the following code

Code Verilog - [expand]1
2
3
4
5
6
7
8
9
10
11
12
integer i;
always @(posedge clk) begin
for (i=0; i<61; i = i+1)
begin
if(data[i+3:i]==4'b0000) begin
occurrences[i]=1'b1;
end
else
occurrences[i]=0;
end

end

It keeps giving me an error in line if(data[i+3:i]==4'b0000) begin
saying 'i' is not a constant.

But when I compare just one bit with
if(data==0)
it synthesizes successfully.

Why is this?
I am just curious why is that comparing for a single bit with i as index is not a problem while I do it for multiple bits i+3:i, its not synthesizable?

or is there anything wrong in the code?

Last edited by a moderator:

#### vGoodtimes

It is an oddity in Verilog. VHDL allows this, so the idea is synthesizable. You can still do this using a for generate, with "i" as the genvar.

##### Super Moderator
Staff member
It is an oddity in Verilog. VHDL allows this, so the idea is synthesizable. You can still do this using a for generate, with "i" as the genvar.

This is incorrect.

The problem is the width of the slice must be a constant. The slice width is defined as follows:

[some_starting_index +: slice_width_constant]

Therefore in your case you should have written:

Code Verilog - [expand]1
2
3
4
5
6
// use this...
if(data[i +:4]==4'b0000) begin  // +:4 is the width of the slice starting at i so i==0 => 3:0
// the [i+3 -:4] would be // i==0 starts at 3 and goes down to 0 (-:4) => 3:0

if(data[i+3:i]==4'b0000) begin

Points: 2

Points: 2

### Sarathkumarkj

Points: 2
Status
Not open for further replies.