Verilog Doubt in coding of D Flip Flop

[Plzhelp]

Can I assign a wire value to a reg variable??

Is this code for a D- FF correct:

---

Code Verilog - [expand]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
module dffnik(input clk,rst,S, output reg q); 
wire d, iwx,iwy;
always@(posedge clk,posedge rst,posedge S)
begin 
assign d<= iwx;
if (rst)
q<=0;
else if (clk && S)
begin
q<=S;
iwy<=q;
end
else
begin q<=d;
iwy<=q;
end
end
endmodule

---

Where iwx is coming from a previous D- FF and iwy is going to the next D-FF. I don't have the Xilinx software with me. If somebody could help me 2 know whether the code is correct or not, it will be of great help.

Thank you in advance.:smile::smile:

 

[imbichie]

Hi,

This may helps you..

D Flip Flop

 

[Plzhelp]

Well.. Thank you for that code of D- FF but I know that code. I was actually trying to create a sub module which uses a D-FF with a set and a reset pin which can be instantiated for the code of ring counter. That is the reason I am using iwx and iwy. Can you plz help me now????

 

[imbichie]

Hi,

Actually whats this iwx and iwy here.

The code seems to be like that the iwy is always 'd' and the iwx is "UNKNOWN"...

And one another thing is that the UNKNOWN iwx is assign to 'd', so 'd' also get unknown....

 

[golden_star]

You can not write assign statement inside a always block. When you write always@(posedge clk) that indicates it is a sequential block but assign statement is a combinational statement.

Can I assign a wire value to a reg variable??

Is this code for a D- FF correct:

---

Code Verilog - [expand]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
module dffnik(input clk,rst,S, output reg q); 
wire d, iwx,iwy;
always@(posedge clk,posedge rst,posedge S)
begin 
assign d<= iwx;
if (rst)
q<=0;
else if (clk && S)
begin
q<=S;
iwy<=q;
end
else
begin q<=d;
iwy<=q;
end
end
endmodule

---

Where iwx is coming from a previous D- FF and iwy is going to the next D-FF. I don't have the Xilinx software with me. If somebody could help me 2 know whether the code is correct or not, it will be of great help.

Thank you in advance.:smile::smile:

 

[FvM]

I was actually trying to create a sub module which uses a D-FF with a set and a reset pin which can be instantiated for the code of ring counter. That is the reason I am using iwx and iwy.

All connections to a module need to go through the interface. In your code iwx is simply unconnected and thus has an unknown state.

 

[Plzhelp]

Golden_star,

Thank you for that tip.. I will remember that..

---------- Post added at 23:29 ---------- Previous post was at 23:25 ----------

FVM and imbichie,

I found out the faults in the my code. The approach itself was wrong.. Thank you guys...