Can I assign a wire value to a reg variable??
Is this code for a D- FF correct:
Code Verilog - [expand] |
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| module dffnik(input clk,rst,S, output reg q);
wire d, iwx,iwy;
always@(posedge clk,posedge rst,posedge S)
begin
assign d<= iwx;
if (rst)
q<=0;
else if (clk && S)
begin
q<=S;
iwy<=q;
end
else
begin q<=d;
iwy<=q;
end
end
endmodule |
Where iwx is coming from a previous D- FF and iwy is going to the next D-FF. I don't have the Xilinx software with me. If somebody could help me 2 know whether the code is correct or not, it will be of great help.
Thank you in advance.:smile::smile: