[SOLVED] VERILOG (divide by zero condition)

[dipin]

hi
i am designing an alu using verilog .in alu ,in division, how can i handle divide by zero condition. in this

$display("error");

is not allowed. can i do anything with high impedence state 'z'.
or do i need to use any flags i hardware.

plz help me im confused .in internet they are saying that u need to do it in hard ware
thanks & regards,

 

[ads-ee]

Let me venture a guess...you've been writing software and thought to yourself Verilog looks like C and I'm good at software so I can now write Verilog software for FPGAs?

Well let me tell you. No it's not for writing software programs. Verilog and VHDL are hardware description languages so unless you know what the underlying logic circuit looks like you shouldn't be writing code.

You should also study the LRM or tutorials and understand the difference between synthesizable and non-sythesizable constructs.
$display is not synthesizable it's a simulation task to show a text string to the simulator's standard out. As you've read elsewhere you need to generate a hardware status flag.

Regards