~ performs bitwise negation whereas ! is a logical operator. In this case both will give u the same result.
Begin has to be used whenver there are multiple statements involved. For eg. if u had to assign values to multiple variables in the if statement u need to use begin. In this case u can skip begin and end. The result wont be affected.
2. Begin and end is for each if or else statement. Not for the if-else structure as a whole. If there are multiple statements under 'IF', use begin-end combination. If and else are to be treated as separate structures.
always @ ( posedge clk or negedge reset)
if (~reset) begin
q <= 1'b0;
else
q <= data;
end
This is not correct becoz begin should have a corresponding end for each of its associated if/else statement..
always @ ( posedge clk or negedge reset)
if (~reset)
q <= 1'b0;
else
q <= data;
Should work in this case since there is only one statement in both if and else.
I don't understand though why "reset" is under "negedge" in the sensitivity list...
The aynchronous reset of a DFF is level sensetive and not edge sensitive...As I see it, the code should be
I don't understand though why "reset" is under "negedge" in the sensitivity list...
The aynchronous reset of a DFF is level sensetive and not edge sensitive...As I see it, the code should be
Tht purely depends on ur application... If the reset is edge triggered use negedge/posedge, else just reset/!reset...Normally for asynchronous resets, just reset is enough....
No. "begin" is for beginning a more generic block of code that has a nice name that I forgot from the formal definitions.... block declaration, that was it. So begin is the beginning of a block declaration. And you can stuff more things inside a block than just assignments.
Random terms you can google: "verilog bnf begin block declaration".
I don't understand though why "reset" is under "negedge" in the sensitivity list...
The aynchronous reset of a DFF is level sensetive and not edge sensitive...As I see it, the code should be