[SOLVED] Verilog: Design counter using adders

[akipro]

The following is one simple 4 bit up counter verilog code I made using a 4 bit adder verilog code ( a working file , tested). I happens that when I include the adder instantiation the clock stops working and hence entire code stops working. Any suggestions of what possibly went wrong????

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Code Verilog - [expand]
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module four_bit_counter(
 
output reg [3:0] a
);
 reg clock ;
 reg [3:0] temp;   // wire [3:0] temp;
 initial
 begin
    a = 4'b0000;
    clock =0 ;
    temp = 4'b0000;  // remove this
 end
 
 four_bit_adder add(.a(temp), .b(4'b0001), .s(a));  // four_bit_adder add(.a(a), .b(4'b0001), .s(temp)); [ Ensure o/p of adder is of type wire ]
 
 always  begin 
    #10 clock = ~clock;
 end
 
 always @(posedge clock) 
    begin 
        assign temp = a;  //   a<=temp;
    end
endmodule

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[mrflibble]

Do you have the screenshot of that simulation?

 

[rberek]

Also note that you cannot use assign in an always block. When you use an assign statement, it is a continuous assignment and thus cannot be further defined by saying assign only on posedge clock.

r.b.

 

[mrflibble]

Indeed. Ditch the assign and the =, and use <= instead.

 

[akipro]

Found the problem, I was not thinking of it as hardware, but as a normal C problem with variables. Instead thought of the hardware first and then made its verilog code. Am commenting the changes made which made it work.

- - - Updated - - -

Indeed. Ditch the assign and the =, and use <= instead.

What is he differnece b/w " = " and " <= " ???

 

[mrflibble]

blocking vs non-blocking assignment <== google that