laserbeak43
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verilog bidirectional port
Hi,
I'm reading a Verilog book and i'm at a point where i'm learning about port declarations. My problem is, that it looks like the port, q, in the code that i'm looking at seems to be declared twice?
is this legal? do you have to declare q an output before you can declare it a reg?
i thought a reg had to be an output anyway?
Hi,
I'm reading a Verilog book and i'm at a point where i'm learning about port declarations. My problem is, that it looks like the port, q, in the code that i'm looking at seems to be declared twice?
Code:
module DFF(q, d, clk, reset);
output q;
reg q; // Output port q holds value; therefore it is declared as reg.
input d, clk, reset;
...
...
endmodule
is this legal? do you have to declare q an output before you can declare it a reg?
i thought a reg had to be an output anyway?