Verilog-counter-values counted from 0 to 127 and then it starts from -128 to 0

[kpraneethin007]

Hi I have designed a 8-bit counter using verilog.
I simulated it using modelsim. counter is performing it's function correctly till the total event at the output reaches 127 (i.e after counting 127 clock cycles)
but after 127 I am getting a value of -128, then -127,126,-125 and so on for each additional clock cycle.
why it is going to -128, why not 129 ?
when I convert decimal to binary value I am getting values correctly in an incremental order, eg: 1111111(127) then for the next clock cycle I am getting 10000000 and so on. Why the same is not happening in case of decimal values?

I have attached the waveform below

Thanks for the reply

 

[mrflibble]

This is purely due to the way you tell modelsim to display the variable. As you noticed after 01111111 (127) you get 10000000 (128). But it so happens that 10000000 is -128 in signed decimal notation for 8 bits. You know, 2s complement notation and all that. So your counter is working fine.

Hope that helps.

 

[kpraneethin007]

This is purely due to the way you tell modelsim to display the variable. As you noticed after 01111111 (127) you get 10000000 (128). But it so happens that 10000000 is -128 in signed decimal notation for 8 bits. You know, 2s complement notation and all that. So your counter is working fine.

Hope that helps.

Thanks a lot!!