verilog code to generate random sequence

[rashmi.kotagiri]

hiii, how to write verilog code for pseudo random interleaver or else how to generate random sequence in verilog?
anybody know.. plz help me.. very urgent

 

[nitu]

Hi..

You can find it link below. You need to register to get it.

https://www.opencores.org/project,systemc_rng

Hopes this help..

 

[ljxpjpjljx]

why not use sc or sv to generate random sequence?

 

[eChipDesign]

An LFSR can be used to generate random values in case of RTL.

In case of verification you can use $random.
In the case define a MIN and MAX values and get
MIN + {$random(seed)}%(MAX-MIN+1)

e.g.
integer pkt_size_max, pkt_size_min, pkt_size;

pkt_size_max = 100;
pkt_size_min = 10;

for ( i = 0; i < 10; i = i + 1) begin
pkt_size = pkt_size_min + {$random(seed)} % (pkt_size_max-pkt_size_min+1)
$display("Generated packet size is %d". pkt_size);
end

The above code will return random packet values between 10 and 100.
To bring constraint random technique into verilog, you can change the values of pkt_size_max and pkt_size_min from the testcase.

Cheers,
eChipDesign