Hello all.
I am a beginner in verilog language. I wrote a code for ring counter using "genvar". But during compilations i am getting an error. I am using vim editor and Modelsim for simulations. Can anyone please spare some time and show me the right way.
Design code is
Notice anything wrong? i.e. the input to the DFF is always bit-3
Besides this your clock generation as written in your testbench won't work
Code Verilog - [expand]
1
forever clk =~clk;
will cause the simulator to reach an iteration limit and error out as there is no time control in that statement. You need to add a #Half_the_clock_period before the LHS of the assignment.
I just wanted to make the code more generalized so that if needs to make it 8 digit so not much shouldn't be change in the design code. So I tried to use "genvar".