verilog code for 8-bit array multiplier

[Mohammed Yameen Musharruf]

Hi,
I'm looking for a verilog code for array multipliers(8,16-bit)
can anyone plz help me out...i'm having trouble writing the code plz help me out...
Thank you

 

[rajavel.rv]

Hi,

what trouble u have to written this array multipliers, having a verilog code or concept, send your written-ed verilog code.

Regards,
Rajavel

 

[chandrapal1990]

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Code Verilog - [expand]
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module ha(sum,c_out,x,y);  //half adder
   input x,y;
   output sum,c_out;
   assign {c_out,sum}=x+y;
endmodule // ha
module fa(sum,c_out,c_in,x,y);  //full adder
   input x,y,c_in;
   output sum,c_out;
   assign {c_out,sum}=x+y+c_in;
endmodule
module partial(x,z,r0,r1,r2,r3,md,mr);  
   input[3:0] x,z;
   input[3:0] mr,md;
   output [7:0] r0,r1,r2,r3;
   reg [7:0]    r0,r1,r2,r3;
   reg [3:0] comp;
   reg  [7:0] tmp;
 
    always@(x or z or mr or md)
      begin
    comp=~mr+1; 
    tmp=comp<<1;
   //r0
    if (~(x[0]|z[0]))
      r0=0;
    else if (~x[0]&z[0])
      begin
         if(mr[3]) r0=mr|8'b11110000;
         else r0=mr;
      end
    else if (x[0]&z[0])
      begin
            if(comp[3])  r0=comp|8'b11110000;
         else r0=comp;
      end
    //r1
    if (~(x[1]|z[1]))
      r1=0;
    else if (~x[1]&z[1])
      begin
         if(mr[3]) r1=(mr|8'b11110000)<<1;
         else r1=mr<<1;
      end
    else if (x[1]&z[1])
      begin
         if(comp[3])  r1=(comp|8'b11110000)<<1;
         else r1=comp<<1;
      end
    //r2
    if (~(x[2]|z[2]))
      r2=0;
    else if (~x[2]&z[2])
      begin
         if(mr[3]==1) r2=(mr|8'b11110000)<<2;
         else r2=mr<<2;
      end
    else if (x[2]&z[2])
      begin
            if(comp[3])  r2=(comp|8'b11110000)<<2;
         else r2=comp<<2;
      end
 
    //r3
    if (~(x[3]|z[3]))
      r3=0;
    else if (~x[3]&z[3])
      begin
         if(mr[3]) r3=(mr|8'b11110000)<<3;
         else r3=mr<<3;
      end
    else if (x[3]&z[3])
      begin
            if(comp[3])  r3=(comp|8'b11110000)<<3;
         else r3=comp<<3;
      end
      end
endmodule// Verilog HDL for "ee103", "partial_generator" "functional"
 
module booth_encoder(mr,md,x,z); 
   input[3:0] mr,md;
   output [3:0] x,z;
   //reg [3:0]  mr,md;
   reg [3:0]    x,z;
   reg [1:0]    i;
   always@(mr or md)
     begin
        
    x[0]=md[0];
    z[0]=md[0];
    x[1]=md[1]&~md[0];
    z[1]=md[1]^md[0];
    x[2]=md[2]&~md[1];
    z[2]=md[2]^md[1];
    x[3]=md[3]&~md[2];
    z[3]=md[3]^md[2];
     end
endmodule // booth_encoder
// Verilog HDL for "ee103", "wallace" "functional"
 
module wallace(r0,r1,r2,r3,result);
   input[7:0] r0,r1,r2,r3;
   output [7:0] result;
   wire [7:0]   result;
   
   wire     w1,w2,w3,w4,w5,w6,w7,w8,w9,w10,w11,w12,w13,w14,w15,w16,w17,w18,w19;
   wire     o1,o2,o3,o4,o5,o6,o7,o8,o9,o10,o11;
   wire     tmp;
   //level 1
   ha ha1(o1,w1,r1[2],r2[2]);
   fa fa2(o2,w2,r2[3],r3[3],r1[3]);
   fa fa3(o3,w3,r1[4],r2[4],r3[4]);
   fa fa4(o4,w4,r1[5],r2[5],r3[5]);
   fa fa5(o5,w5,r1[6],r2[6],r3[6]);
   fa fa17(o10,w16,r0[7],r1[7],r2[7]);
   
   //level 2
   ha ha6(o6,w6,o2,r0[3]);
   fa fa7(o7,w7,w2,o3,r0[4]);
   fa fa8(o8,w8,w3,o4,r0[5]);
   fa fa9(o9,w9,w4,o5,r0[6]);
   fa fa18(o11,w17,w5,o10,r3[7]);
   
   //fast CL A
   not not1(w19,r0[0]);
   not not2(result[0],w19);
   
   ha ha10(result[1],w10,r0[1],r1[1]);
   fa fa11(result[2],w11,w10,r0[2],o1);
   fa fa12(result[3],w12,w11,w1,o6);
   fa fa13(result[4],w13,w12,w6,o7);
   fa fa14(result[5],w14,w13,w7,o8);
   fa fa15(result[6],w15,w14,w8,o9);
   fa fa16(result[7],w18,w15,w9,o11);
endmodule
 
 
 
//`timescale 1ns/10ps
module mul_test1(result,mr,md);
   input[3:0] mr,md;
   output [7:0] result;
   wire [3:0]   x,z;
   wire [7:0]   r0,r1,r2,r3;
   booth_encoder booth(mr,md,x,z);
   partial pp(x,z,r0,r1,r2,r3,md,mr);
   wallace tree(r0,r1,r2,r3,result);
   //$monitor("mr=%b,md=%b,result=%d",mr,md,result);
endmodule

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