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Verilog code error: unable to determine top module

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moustafaali

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salam alikom
hello
i'm new in verilog and need test semple project using logsim
this is the code
/////////////////////////////////////////////////////////////////////////////
//counter project
module counter (clk, reset, enable, count);
input clk, reset, enable;
wire clk, reset, enable;
output count;
reg[3:0] count;
always @ (reset)
begin
if (reset == 1) begin
count <= 0;
end
end
always @ (posedge clk)
begin
if (enable == 1) begin
count <= count + 1;
end
end
endmodule
////////////////////////////////////////////////////////////////////////////
and this is the error appeared
/////////////////////////////////////////////////////////////////////////////
# compilation completed
** Error ** unable to determine top module
 

no_mad

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Re: verilog first code

Hi,

Actually, there are multiple errors here.

Code:
//counter project
module counter (clk, reset, enable, count);

input clk, reset, enable;
wire clk, reset, enable;
output count;    <------- output [3:0] count;
reg[3:0] count;

always @ (reset) <--------I believe u r trying to do async reset not good coding style 
begin
if (reset == 1) begin
count <= 0;
end
end
always @ (posedge clk)
begin
if (enable == 1) begin
count <= count + 1;
end
end
endmodule
Below is the correct way to code it:

Code:
module count (clk, rst, enable, cnt);

input  clk, rst, enable;
output [3:0] cnt;

reg [3:0] cnt;

always @(posedge clk or posedge rst) // async active high reset
begin
     if(rst)
           cnt <= 0;
     else if(enable)
           cnt <= cnt + 1;
end

endmodule
You can learn verilog from any verilog books. One suggestion is Samit Planitkar (sorry if wrong spelling). U can actually search in this forum.

Hope it helps.
 

moustafaali

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Re: verilog first code

no no it is right
all the problem that i didnot make project:D:D:D:D
excuse me this my first project
by the way this sentence is right
and thanks for your modification it is very suitable not large as i write and thanks also for the illustrate of the difference between the sync and async
 

crazyk

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verilog first code

I think good coding style is more important
 

aiko89

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Re: verilog first code

may i know that ur code that have a testbench.. i needed to do for my counter.... hope that ue can help mie... thank you advance....
 

aiko89

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Re: verilog first code

hi anyone there can help...i need your testbench... thank you
 

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