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| `timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 19:18:28 09/24/2016
// Design Name:
// Module Name: SDIO_M
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module SDIO_M(
input clk,
input [7:0] din,
input reset,
input dm_in,
input wr,
input rd,
input miso,
output reg mosi,
output reg cs,
output reg sclk,
output reg [7:0] dout
);
parameter [4:0] rst=5'd0,
init=5'd1,
cmd0=5'd2,
cmd55=5'd3,
cmd41=5'd4,
poll_cmd=5'd5,
idle=5'd6,
read_block=5'd7,
read_block_wait=5'd8,
read_block_data=5'd9,
read_block_crc=5'd10,
send_cmd=5'd11,
receive_byte_wait=5'd12,
receive_byte=5'd13,
write_block_cmd=5'd14,
write_block_init=5'd15,
write_block_data=5'd16,
write_block_byte=5'd17,
write_block_wait=5'd18;
reg [4:0] state,return_state;
integer byte_counter=515;
integer bit_counter=160;
reg sclk_sig;
reg [55:0] cmd_out;
reg [7:0] recv_data;
reg [31:0] address;
reg cmd_mode=1;
reg data_mode=1;
reg response_mode=1;
reg [7:0] data_sig=8'h00;
always @(posedge clk or reset)
begin
data_mode<=dm_in;
if(reset)
begin
state<=rst;
sclk_sig<=0;
end
else begin
case(state)
rst:begin
sclk_sig<=0;
cmd_out<=0;
address<=0;
byte_counter=0;
cmd_mode<=1;
response_mode<=1;
bit_counter=160;
cs<=1;
state<=init;
end
init:begin
if(bit_counter==0)
begin
cs<=0;
state<=cmd0;
end
else begin
bit_counter<=bit_counter-1;
sclk_sig<=~sclk_sig;
end
end
cmd0:begin
cmd_out<=56'hff400000000095;
bit_counter<=55;
return_state<=cmd55;
state<=send_cmd;
end
cmd55:begin
cmd_out<=56'hff770000000001;
bit_counter<=55;
return_state<=cmd41;
state<=send_cmd;
end
cmd41:begin
cmd_out<=56'hff690000000001;
bit_counter<=55;
return_state<=poll_cmd;
state<=send_cmd;
end
poll_cmd:begin
if(recv_data[0]==1'b0)
begin
state<=idle;
end
else begin
state<=cmd55;
end
idle:begin
if(rd)
begin
state<=read_block;
end
else if(wr)
begin
state<=write_block_cmd;
end
else begin
state<=idle;
end
end
read_block:begin
cmd_out<={8'hff,8'h51,address,8'hff};
bit_counter<=55;
return_state<=read_block_wait;
state<=send_cmd;
end
read_block_wait:begin
if(sclk_sig && !miso)
begin
state<=read_block_data;
byte_counter<=511;
bit_counter<=7;
return_state<=read_block_data;
state<=receive_byte;
end
sclk_sig<=~ sclk_sig;
end
read_block_data:begin
if(byte_counter==0)
begin
bit_counter<=7;
return_state<=read_block_crc;
state<=receive_byte;
end
else begin
byte_counter<=byte_counter-1;
return_state<=read_block_data;
bit_counter<=7;
state<=receive_byte;
end
end
read_block_crc:begin
bit_counter<=7;
return_state<=idle;
address<=address+12'h200;
state<=receive_byte;
end
send_cmd: begin
if(sclk_clk)
begin
if(bit_counter==0)
begin
state<=receive_byte_wait;
end
else begin
bit_counter<=bit_counter-1;
cmd_out<={cmd_out[54:0],1'b1};
end
sclk_sig<=~sclk_sig;
end
end
receive_byte_wait:begin
if(sclk_sig)
begin
if(!miso)
begin
recv_data<=8'h00;
end
end
if(!response_mode)
begin
bit_counter<=3;
end
else begin
bit_counter<=6;
end
state<=receive_byte;
sclk_sig<=~sclk_sig;
end
receive_byte: begin
if(sclk_sig)
begin
recv_data<={recv_data[6:0],miso};
end
if(bit_counter==0)
begin
state<=return_state;
dout<={recv_data[6:0],miso};
end
else begin
bit_counter<=bit_counter-1;
end
sclk_sig<=~sclk_sig;
end
write_block_cmd:begin
cmd_mode<=1;
if(!data_mode)
begin
cmd_out<={8'hff,8'h59,address,8'hff};
end
else begin
cmd_out<={8'hff,8'h58,address,8'hff};
end
bit_counter<=55;
return_state<=write_block_init;
state<=send_cmd;
end
write_block_init:begin
cmd_mode<=0;
byte_counter<=515;
state<=write_block_data;
end
write_block_data: begin
if(byte_counter==0)
begin
state<=receive_byte_wait;
return_state<=write_block_wait;
response_mode<=0;
end
// else begin
if(byte_counter==2 or byte_counter==1)
begin
data_sig<=8'hff;
end
// else begin
if(byte_counter==515)
begin
if(!data_mode)
begin
data_sig<=8'hfc;
end
else begin
data_sig<=8'hfe;
end
end
// end
// end
else begin
data_sig<=din;
end
bit_counter<=7;
state<=write_block_data;
byte_counter<=byte_counter-1;
end
write_block_byte: begin
if(sclk_sig)
begin
if(bit_counter==0)
begin
state<=write_block_data;
end
else begin
data_sig<={data_sig[6:0],1'b1};
bit_counter<=bit_counter-1;
end
end
sclk_sig<=~sclk_sig;
end
write_block_wait:begin
response_mode<=1;
if(sclk_sig)
begin
if(miso)
begin
if(!data_mode)
begin
state<=write_block_init;
end
end
end
else begin
address<=address+12'h200;
state<=idle;
end
// end
// end
sclk_sig<=~sclk_sig;
end
// default: begin
// state<=idle;
// end
endcase
end
end
assign sclk=sclk_sig;
assign mosi=(cmd_mode)?cmd_out[55]:data_sig[7];
endmodule
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