Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Verilog Calling Task with Array

Status
Not open for further replies.

ganeshrahate

Newbie level 2
Joined
Feb 19, 2013
Messages
2
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,300
Hi
I am just working on my very first project on verilog in my final year

I am stuck at one task

I am trying create task for writing data on bus , but i want to send multiple data in same task by using one input declaration as an array

task write_data;
input n_write; // nuber of data to be send
input [data_width-1:0] write_data;
begin
wrdataen = 1'b1;
repeat(n_write) @(posedge clk) // i am thinking of using for loop here
begin
$display ("%t : Value Write is %h", $time, write_data);
wrdata = write_data;
end
wrdataen = 1'b0; // this is write data enable
end
endtask


i wan to call task this

write_data(32'h5555,32'h7777,32'h6666,32'h8888,32'h11111,32'h2222)
 

If you can use SystemVerilog, you would code this using a dynamic array:
Code:
task write_data (input [data_width-1:0] write_data[]);
  wrdataen = 1'b1;
  foreach(write_data[i]) @(posedge clk) // i am thinking of using for loop here
  begin
    $display ("%t : Value Write is %h", $time, write_data[i]);
    wrdata = write_data[i];
    end
  wrdataen = 1'b0; // this is write data enable
endtask

write_data({32'h5555,32'h7777,32'h6666,32'h8888,32' h11111,32'h2222});
Otherwise you will have to use a large vector and pull out 32-bits at a time.

Code:
task write_data (input integer n_write, reg [(MAX_WORDS*data_width)-1:0] write_data[]);
integer i;
begin
 wrdataen = 1'b1;
  for(i = 0, i<n_write)i=i+1)
    @(posedge clk) // i am thinking of using for loop here
  begin
    $display ("%t : Value Write is %h", $time, write_data[i*32+:32]); // you'll have to play with this to get the words in the right order
    wrdata = write_data[i*32+:32];
    end
  wrdataen = 1'b0; // this is write data enable
end
endtask
 

    V

    Points: 2
    Helpful Answer Positive Rating
Thank you so much sir
I have been stuck over this for more than 3 weeks and after even long net searching i didnt got any help , but thanks to you sir i have got answer for my query.
If I am not asking too much sir can please refer me some book by which i can enhance my verilog skills more. I have got lots of basic book i am looking for some advance level.
Thank you so much sir.

- - - Updated - - -

Thank you so much sir
I have been stuck over this for more than 3 weeks and after even long net searching i didnt got any help , but thanks to you sir i have got answer for my query.
If I am not asking too much sir can please refer me some book by which i can enhance my verilog skills more. I have got lots of basic book i am looking for some advance level.
Thank you so much sir.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top