Verilog bus contention debug

[beeflobill]

I'm trying to debug a bus contention issue in Verilog. My problem is that I'm having trouble identifying which drivers are contending on the bus. Is there a way to list all the drivers to a wire and what they are attempting to drive? Or, is there a better method for doing this?

By the way, I'm using nc-verilog, but if you have a solution in a different tool I'd still be interested to know because any inputs or concepts would be helpful.

I found a similar question at https://www.edaboard.com/threads/281838/

Thank you.

 

[jrwebsterco]

Synopsys' VCS has a "show drivers" command (or maybe was simply "show" or "drivers") with a path to an object as a parameter.
ModelSim/Questa has a similarly named command.
Both are more easily used in the GUI, via drag-and-drop or else by selecting the target signal in waveform window, clicking on the corresponding icon, etc.
But I also recall you may need to specify some compile-time options to turn-off certain optimizations and/or also enable the UCLI (in the case of VCS).
(but this may already be the case if you are interactively debugging in a GUI-mode)

I'd be very surprised if nc-verilog does not offer a similar debug facility - I do not have access to that simulator.
It should be at least touched-upon in the GUI/Users Manual.