verilog : booth multiplier

[BIPINLIKHAR]

Hi,
i m working on booth multiplier , everything is working, but last four assignment statements are not giving proper results.

module newproj (a,b,rslt,rslt1,rslt2,rslt4,rslt3,xyz,xyz1,xyz2,xy z3);
input [7:0] a;
input [7:0] b;
output [15:0] rslt;
output [15:0] rslt1;
output [15:0] rslt2;
output [15:0] rslt3;
output [15:0] rslt4;

output [8:0] xyz;
output [8:0] xyz1;
output [8:0] xyz2;
output [8:0] xyz3;

wire [8:0] y;

wire sg;
wire sg1;
wire sg2;
wire sg3;
assign y[0]=0;
assign y[8:1]=b[7:0];
assign rslt4=16'b0000000000000000;

struc a1(xyz,sg,a,y[2:0]);
struc a2(xyz1,sg1,a,y[4:2]);
struc a3(xyz2,sg2,a,y[6:4]);
struc a4(xyz3,sg3,a,y[8:6]);

assign rslt = xyz;
assign rslt1 = xyz1<< 2;
assign rslt2 = xyz2<< 4;
assign rslt3 = xyz3<< 6;

assign rslt1[0]= sg;
assign rslt2[2]= sg1;
assign rslt3[4]= sg2;
assign rslt4[6]= sg3;
endmodule