[SOLVED] verilog beginner for loops

[cloud9Z9]

module fori(A,B);
input [0:5] A;
output [0:5] B;
wire [0:5]A;
reg [0:5]B;
reg i=0;
initial begin
for(i=0;i<6;i=i+1)begin
B[i]=A[i];
end
//B[4]=1'b1;
end
initial begin
$monitor("OR=%b, AND=%b, IN=%b, time=%t\n",B,A,$time);
end
endmodule

module tb_fori();
reg [0:5]A;
wire [0:5]B1;
fori fori1(.A(A),.B(B1));
initial
  begin

A[0:5] <=6'b000001;
#10;

A[0:5] <= 6'b100001;
#10;

A[0:5] <= 6'b00011;
#10;

$finish;
end
initial begin
$monitor("OR=%b, AND=%b, IN=%b, time=%t\n",B1,A,$time);
end
endmodule

can we assign the B[4] after the for loop? like i did ....and pls tell me wats wrong with my code it compiles but doesnt give any output when i ./a.out it

 

[tariq786]

I think you can't do
reg i=0;

secondly its only one bit. Try first with reg [2:0] but dont' write reg[2:0] = 3'b000; For loop takes care of it automatically.

OR

use the following instead
integer i; //do not use integer i = 0;

 

[cloud9Z9]

I think you can't do
reg i=0;

secondly its only one bit. Try first with reg [2:0] but dont' write reg[2:0] = 3'b000; For loop takes care of it automatically.

OR

use the following instead
integer i; //do not use integer i = 0;

/*-------------- LD_PC -------*/
/**/
/**/ initial begin
/**/
/**/  //-- Initialize to 0.
/**/  for( i = 0; i < 64; i = i + 1) begin
/**/    LD_PC[i] = 1'b0;
/**/  end
/**/LD_PC[18]=1'b1;
/**/  //-- Set non-zero as needed.
/**/ end

can i do this ?? i just need to set LC_PC[18] to 1.

 

[tariq786]

Yes you can do this. only LD_PC will be 1

 

[cloud9Z9]

Yes you can do this. only LD_PC will be 1

U mean LD_PC[18]. Anyway thanx for the quick reply.