Verilog beginner doubts

[Raagasudha]

Hi,

I wrote a design and testbench code for PIPO shift register. I have instantiated four dflops in the design. I noticed something strange.. If I use this construct in the testbench:

always
----
----
I=I+1;
if(I==20) $finish;
end

the compilation is fyn but the execution sends it to infinite loop. Can anyone tell me why this is happening? The code is working fyn if I use #80 $finish; in its place. I am facing the same problem for SISO design also.

 

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I've tried a few things with the following code and I can't get it to fail in the way you are suggesting.

module temp3;
integer I = 0;
always
begin
  I = I + 1;
//  # 1;
//  $display ("%d", I);
  if (I==20) $finish;
end
endmodule

You'll have to post the complete code and the transcript window contents of the compilation etc.

You should have posted the code with the begin following the always. Those not familiar with Verilog would probably not know they have to add it for the code to compile.

With the $display uncommented it counts from 1 through 20 and completes in 0 fs as there is no delays involved.
With the # 1; uncommented it counts from 1 through 20 and completes in 20 ns (with default timescale of 1ns/1ns).

Regards

 

[Raagasudha]

ok, here is the code that is hanging:
-----------------------------------------------------------------------------------------------

---

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module sipo_tb;
reg d,clk,clr,reset,check;
wire q1,q2,q3,q4;
reg [3:0]t;
integer i;
 
sipo dut1(.d(d), .q1(q1),.q2(q2), .q3(q3), .q4(q4), .clk(clk), .clr(clr), .reset(reset)); 
 
initial
begin
clk = 1'b0;
clr = 1'b0;
reset = 1'b0;
d = 0;
end
 
always
begin
forever
#10 clk = ~clk;
repeat(5)@(negedge clk)
begin
reset = 0;
clr = 0;
d = $random;
t[i] = d;
i=i+1;
if(i>3)
begin
check = 1;
i = 0;
end
end
$finish;  
end
always@(posedge clk)
begin
if( check )
begin
if(t[0] !== q1 && t[1] !== q2 && t[2] !== q3 && t[3] !== q4)
$display(" error mismatch: %b%b%b%b",t[0],t[1],t[2],t[3]," output is %b%b%b%b",q1,q2,q3,q4);
check = 0;
end
end
 
endmodule

---

-----------------------------------------------------------------------------------------------------------

I still haven't figured out why its hanging yet. Please help..

 

[Raagasudha]

Also, while forcibly breaking the simulation, the execution is at the clock inversion line (clk = ~clk). There are no warnings or errors in compilation

 

[kommu4946]

Also, while forcibly breaking the simulation, the execution is at the clock inversion line (clk = ~clk). There are no warnings or errors in compilation

I think problem is with forever statement in your code..
The forever instruction continuously repeats the statement that follows it. Therefore, it should be used with procedural timing controls (otherwise it hangs the simulation).either you write it in separate always block or initial block.

always begin
  forever #10 clk = ~clk;
end

initial begin
              clk = 1'b0;
              forever #10 clk = ~clk; // the clock flips every 10 time units.
           end

 

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I think problem is with forever statement in your code..

There's no need to guess. The forever is the problem. A forever should alway be placed in a separate initial block as it stops further execution beyond statement following the forever.

I also don't see any reason for all the extra begins after the first one that follows the first always.

- - - Updated - - -

FYI here is the standard template for generating a clock in a testbench.

initial begin
  clk = 0;
  forever #10 clk = ~clk;
end

Ther should be nothing else in this initial block. If you have anotther clock tp generate use another initial block.