Feb 6, 2009 #1 B balan Member level 2 Joined Feb 18, 2007 Messages 44 Helped 0 Reputation 0 Reaction score 0 Trophy points 1,286 Activity points 1,518 basics of verilog module Top; reg[3:0] r; initial begin r = 4'b1110; $display(" r = %b ", r); $display("(3'b01x ? 4'b01xz : r) = %b ", (3'b01x ? 4'b01xz : r)); $display("(3'b01x ? 4'b01xz : 4'b0000) = %b ", (3'b01x ? 4'b01xz : 4'b0000)); $display("Both values should be identical: 01xz"); end enmodule. Can anyone suggest what would be the output of the above example.
basics of verilog module Top; reg[3:0] r; initial begin r = 4'b1110; $display(" r = %b ", r); $display("(3'b01x ? 4'b01xz : r) = %b ", (3'b01x ? 4'b01xz : r)); $display("(3'b01x ? 4'b01xz : 4'b0000) = %b ", (3'b01x ? 4'b01xz : 4'b0000)); $display("Both values should be identical: 01xz"); end enmodule. Can anyone suggest what would be the output of the above example.
Feb 6, 2009 #2 RBB Full Member level 5 Joined Jul 2, 2007 Messages 303 Helped 71 Reputation 142 Reaction score 36 Trophy points 1,308 Location USA Activity points 2,560 verilog basics r = 1110 (3'b01x ? 4'b01xz : r) = 01xz (3'b01x ? 4'b01xz : 4'b0000) = 01xz Both values should be identical: 01xz
verilog basics r = 1110 (3'b01x ? 4'b01xz : r) = 01xz (3'b01x ? 4'b01xz : 4'b0000) = 01xz Both values should be identical: 01xz
Feb 7, 2009 #3 B balan Member level 2 Joined Feb 18, 2007 Messages 44 Helped 0 Reputation 0 Reaction score 0 Trophy points 1,286 Activity points 1,518 Re: verilog basics Thanks RBB. Can you please explain how does it work. i have confusion in understanding the flow.
Re: verilog basics Thanks RBB. Can you please explain how does it work. i have confusion in understanding the flow.
Feb 7, 2009 #4 RBB Full Member level 5 Joined Jul 2, 2007 Messages 303 Helped 71 Reputation 142 Reaction score 36 Trophy points 1,308 Location USA Activity points 2,560 verilog basics The line $display(" r = %b ", r); is fairly self-explanatory since r is 4'b1110. The next two lines use the Ternary operation. Look on Wikipedia if you don't understand this operation. Since 3'b01x is true then the value 01xz is output to the screen. The 3'b01x is true because 0 | 1 | x (bitwise OR) is 1, so true
verilog basics The line $display(" r = %b ", r); is fairly self-explanatory since r is 4'b1110. The next two lines use the Ternary operation. Look on Wikipedia if you don't understand this operation. Since 3'b01x is true then the value 01xz is output to the screen. The 3'b01x is true because 0 | 1 | x (bitwise OR) is 1, so true