verilog basics - output of example

[balan]

basics of verilog

module Top;
reg[3:0] r;

initial begin
r = 4'b1110;
$display(" r = %b ", r);
$display("(3'b01x ? 4'b01xz : r) = %b ", (3'b01x ? 4'b01xz : r));
$display("(3'b01x ? 4'b01xz : 4'b0000) = %b ", (3'b01x ? 4'b01xz : 4'b0000));
$display("Both values should be identical: 01xz");

end
enmodule.

Can anyone suggest what would be the output of the above example.

 

[RBB]

verilog basics

r = 1110
(3'b01x ? 4'b01xz : r) = 01xz
(3'b01x ? 4'b01xz : 4'b0000) = 01xz
Both values should be identical: 01xz

 

[balan]

Re: verilog basics

Thanks RBB. Can you please explain how does it work. i have confusion in understanding the flow.

 

[RBB]

verilog basics

The line
$display(" r = %b ", r);
is fairly self-explanatory since r is 4'b1110.

The next two lines use the Ternary operation. Look on Wikipedia if you don't understand this operation.

Since 3'b01x is true then the value 01xz is output to the screen. The 3'b01x is true because 0 | 1 | x (bitwise OR) is 1, so true