Verilog Assignment with condition

beginner_EDA · Feb 21, 2019

Code Verilog - [expand]
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always @(posedge clk) begin
 
    x<=1'b1;     //  First Assignment
      if (y) begin    //some condition met
        x <= 1'b1;  // Second Assignment
      end
 
end

I would like to know in above code when also condition met which assignment will be executed although both assignments are same? First Assignment or Second Assignment?

std_match · Feb 21, 2019

It doesn't matter that both assigments are identical. Only the second assignment is used if the condition "y" is true.

dave_59 · Feb 21, 2019

If there is clear execution ordering of a set of nonblocking assignments, the order of the resulting updates to the LHS are preserved. So the second assignment overrides the first.

In synthesis, the conditional statement would be optimized away as it has no impact on the result.

Verilog Assignment with condition

beginner_EDA

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std_match

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dave_59

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Code Verilog - [expand]
1 2 3 4 5 6 7 8	always @(posedge clk) begin x<=1'b1; // First Assignment if (y) begin //some condition met x <= 1'b1; // Second Assignment end end

Verilog Assignment with condition

beginner_EDA

Full Member level 4

std_match

Advanced Member level 4

dave_59

Advanced Member level 3

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