[verilog] assign wire to register in loop

yoran · May 15, 2010

Hey,

I have a question about Verilog. I have a bunch of wires h_in[016*640)-1] as an input in a module. They represent 640 values of 16 bits. I want to store those into registers, so

Code:

reg signed [0:16-1] h[0:639];

h[0] <= h_in[0*16:(0+1)*16-1];
h[1] <= h_in[1*16:(1+1)*16-1];
h[2] <= h_in[2*16:(2+1)*16-1];
h[3] <= h_in[3*16:(3+1)*16-1];
h[4] <= h_in[4*16:(4+1)*16-1];
...
h[638] <= h_in[638*16:(638+1)*16-1];
h[639] <= h_in[639*16:(639+1)*16-1];

I tried to make this more generic using a for-loop and generate for-loop but I couldn't succeed. How can I write this using a loop statement?

Thanks,
Yoran

RBB · May 15, 2010

You'll need to try something like this...

Code:

module myBuf(Q, A);
   output[15:0] Q;
   input [15:0] A;

   assign Q = A;
endmodule
   
module foo(h_in);
   input [0:(16*640)-1] h_in;
   
   wire [0:16-1] 	h[0:639]; 
   
   genvar 	i;
   generate
      for(i = 0; i < 640; i = i + 1)
         begin : b1
            myBuf ibuf(h[i], h_in[i*16:(i+1)*16-1]);
         end
   endgenerate
endmodule

yoran · May 16, 2010

Thanks for the reply. So you kind of have to create this "artificial" module to make it work? Maybe it's because generate statements only work for module instantiation?

RBB · May 16, 2010

Yes. And you can't use a for loop because Verilog requires constant indexes in for loops.

[verilog] assign wire to register in loop

yoran

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yoran

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[verilog] assign wire to register in loop

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