Hi guys,
Well, upon your suggestions I tried various incarnations of the idea, eventually merging this module with a timing generation module and ohping the compiler/fitter would manage to work out the optimisations better than I can.
Turns out it was optimised for 'speed' rather than 'area'. With that changed the max clock dropped form 120MHz, to 60 - which is fine since I'm looking at 16-24MHz
Macrocells went from 32, down to 23 (!!) so I'm not sure if that means tQuartus is very good at optimsing for speed, or very good for area. Either way, its 3 more than lattice. I relaise comparing different compilers is meaningless because its all down to the device used - and different manufacturers have differen macrocell structures. But comparing the two, they looked painfully similar in terms of register configuration and product-terms.
Anyways, seems the software I use (Quartus, ispLEVER, and ISEwebpack) are all pretty sensitive to verilog coding style. Example, clocking an 8-bit counter from a combinatorial output, or another register adds 4 macrocells to the design. But clcking it form the main clock (which is hardware routed throughout the chip as its global) and using 'if <something>' doesn't increase the resource usage at all. I imagine thats the input AND array kicking in.
All in all, very steep learning curve for me over the past few days but I'm extremely impressed with the versatility of verilog. As I said, I started with ABEL, which is simple and *can* be used for complicated designs, but verilog seems much more modular (even modular within a single module..).
As for the actual application. Currently using 53 MC's for a 320x240 256 colour STN display controller with 1MBit ram and no write buffer. With a 128-MC device, that leaves plenty of space for the write buffer (data and address), as well as a couple of configuration registers - something I didn't think a small CPLD could do as its really FPGA territory. Once my website is up, I'll post the designs on there, If anything might be helpful to those who want to see just what small CPLD's can do instead of the usual 'counters and buffers'.
j_andr.
Thanks for the code! I'll pop it in Quartus tomorrow and see what happens. I believe you've gone about it differently than myself, perhaps with fewer resources! I shall post my modified version (without all the timing) and we can compared speed/resource usage.
Interesting that there is very little info on controlling colour STN displays. I guess TFT's with their faster response, better contrast and *much* easier driving characteristics took over some years ago. At the bottom end, theres monochrome STN, at the top, theres 24-bit TFT's. The middle ground generally isn't covered by DIY folk.
Thanks agian people.
Buriedcode