I have a code where I have an array of registers mainreg having sixteen registers, I want to consider the first block of 8 registers from 0 - 7 from these 8 i want to separate 2 pairs of register arrays having 4 registers each and then again do the same thing from the next block of 8 registers.
Thus say mainreg has 0 - 15, I will consider the first 8, 0 - 7 and bifurcate them into two registers 'a' having 4 regs and 'b' having four and again the same thing for the next block of 8 registers.
The formula for the bifurcation of 4 registers from a block of 8 registers is as follows :
the block of 8 regs has : 0 1 2 3 4 5 6 7
the first array 'a' will have : 0 3 5 6 (starting from 0 do +3, +2, +1)
the second array 'b' will have : 7 4 2 1 (starting from 7 do -3, -2, -1)
and the again for the next block of 8 regs has : 8 9 10 11 12 13 14 15
'a' will have : 8 11 13 14
'b' will have : 15 12 10 9
thus I have one counter c1 which will count the no of blocks having 8 regs here it is 16/8 = 2 therefore c1 should operate from 0 < 2
for first block of 8 regs c1 = 0
another counter for incrementing 3, 2, 1 starting from 0 finishing at 7
another counter for decrementing 3, 2, 1 starting from 7 finishing at 0
and then for the next block of 8 registers (starting from 8 to 15) c1 = 1
c2 = c2+2 = 8
c3 = c3+14 = 15
I have written the code :
`timescale 1ns / 100ps
module mainreg (clk, nReset);
input clk, nReset;
wire clk;
wire nReset;
parameter n=16;
// S0=0, S1=1, S2=2, S3=3, S4=4;
reg [15:0] c1;
reg [15:0] c2;
reg [15:0] c3;
// integer c1, c2, c3;
// reg [2:0] state;
wire [15:0] mainreg [0:n-1];
reg [15:0] a [0:3];
wire [15:0] b [0:3];
assign mainreg[0]= 0;
assign mainreg[1]= 1;
assign mainreg[2]= 2;
assign mainreg[3]= 3;
assign mainreg[4]= 4;
assign mainreg[5]= 5;
assign mainreg[6]= 6;
assign mainreg[7]= 7;
assign mainreg[8]= 8;
assign mainreg[9]= 9;
assign mainreg[10]= 10;
assign mainreg[11]= 11;
assign mainreg[12]= 12;
assign mainreg[13]= 13;
assign mainreg[14]= 14;
assign mainreg[15]= 15;
always @(posedge clk or negedge nReset)
if (!nReset)
begin
a[0] = 0;
a[1] = 0;
a[2] = 0;
a[3] = 0;
b[0] = 0;
b[1] = 0;
b[2] = 0;
b[3] = 0;
c1 = 0;
c2 = 0;
c3 = 7;
end
else
if (c1 < 2)
begin
a[0] = mainreg[c2];
b[0] = mainreg[c3];
a[1] = 0;
b[1] = 0;
a[2] = 0;
b[2] = 0;
a[3] = 0;
b[3] = 0;
c2 = c2 + 3;
c3 = c3 - 3;
a[1] = mainreg[c2];
b[1] = mainreg[c3];
a[2] = 0;
b[2] = 0;
a[3] = 0;
b[3] = 0;
c2 = c2 + 2;
c3 = c3 - 2;
a[2] = mainreg[c2];
b[2] = mainreg[c3];
a[3] = 0;
b[3] = 0;
c2 = c2 + 1;
c3 = c3 - 1;
a[3] = mainreg[c2];
b[3] = mainreg[c3];
c2 = c2 + 2;
c3 = c3 + 14;
c1 = c1 + 1;
end
else
begin
a[0] = 0;
a[1] = 0;
a[2] = 0;
a[3] = 0;
b[0] = 0;
b[1] = 0;
b[2] = 0;
b[3] = 0;
end
endmodule
It is simulating fine to give two arrays :
a : 0 3 5 6
b : 7 4 2 1
and
a : 8 11 13 14
b : 15 12 10 9
but I am having problems in synthesizing as it says array delacration is oversize in a[0]=manireg[c2];
I have used non-blocking also but it gives wrong result.
I wrote in a state machine format but it synthesis to latches :
`timescale 1ns / 100ps
module mainreg (Clk, nReset);
input Clk, nReset;
wire Clk;
wire nReset;
parameter n=16, S0=0, S1=1, S2=2, S3=3, S4=4;
//reg [15:0] c1, c2, c3;
integer c1, c2, c3;
reg [2:0] state;
wire [15:0] mainreg [0:n-1];
reg [15:0] a [0:3];
reg [15:0] b [0:3];
assign mainreg[0]= 0;
assign mainreg[1]= 1;
assign mainreg[2]= 2;
assign mainreg[3]= 3;
assign mainreg[4]= 4;
assign mainreg[5]= 5;
assign mainreg[6]= 6;
assign mainreg[7]= 7;
assign mainreg[8]= 8;
assign mainreg[9]= 9;
assign mainreg[10]= 10;
assign mainreg[11]= 11;
assign mainreg[12]= 12;
assign mainreg[13]= 13;
assign mainreg[14]= 14;
assign mainreg[15]= 15;
always @(posedge Clk or negedge nReset)
if (!nReset)
state <= S0;
else
begin
if (c1 < 2)
case(state)
S0 : begin
state <= S1;
end
S1 : begin
state <= S2;
end
S2 : begin
state <= S3;
end
S3 : begin
state <= S4;
end
S4 : begin
state <= S1;
end
endcase
end
always @(state,c1,c2,c3)
begin
case(state)
S0 : begin
a[0] = 0;
a[1] = 0;
a[2] = 0;
a[3] = 0;
b[0] = 0;
b[1] = 0;
b[2] = 0;
b[3] = 0;
c1 = 0;
c2 = 0;
c3 = 7;
end
S1 : begin
a[0] = mainreg[c2];
b[0] = mainreg[c3];
a[1] = 0;
b[1] = 0;
a[2] = 0;
b[2] = 0;
a[3] = 0;
b[3] = 0;
c2 = c2 + 3;
c3 = c3 - 3;
end
S2 : begin
a[1] = mainreg[c2];
b[1] = mainreg[c3];
a[2] = 0;
b[2] = 0;
a[3] = 0;
b[3] = 0;
c2 = c2 + 2;
c3 = c3 - 2;
end
S3 : begin
a[2] = mainreg[c2];
b[2] = mainreg[c3];
a[3] = 0;
b[3] = 0;
c2 = c2 + 1;
c3 = c3 - 1;
end
S4 : begin
a[3] = mainreg[c2];
b[3] = mainreg[c3];
c2 = c2 + 2;
c3 = c3 + 14;
c1 = c1 + 1;
end
endcase
end
endmodule