sujithchakra
Junior Member level 1
Hi,
Can someone tell me if we can synthesize Verilog and VHDL files together into a netlist in Verilog using Cadence PKS tool?
Thanks,
Sujith Chakra
Can someone tell me if we can synthesize Verilog and VHDL files together into a netlist in Verilog using Cadence PKS tool?
Thanks,
Sujith Chakra