MicroElec
Newbie level 4
Verilog and SDF
Hi Guys,
I am simulating verilog model using an SDF file which cotains delays between (a,b) and (a,c)
The verilog model is containing this specify
// Delays
(a=> b)= (0,0);
(a => c)= (0,0);
As you may know the real delay between (a,b) and (a,c) in SDF will replace (0,0) in the verilog model.
My question:
I do not want to use the delay (a,b) and (a,c)
I have internal signals called e,f for , and I want to use a delay (e,b) and (f,c)
with delay (a,b)=(e,b) and (a,c)=(f,c).
So, what can I add to my verilog model to make delays (a,b)=(e,b) and (a,c)=(f,c).
I am beginner,
thank you
Hi Guys,
I am simulating verilog model using an SDF file which cotains delays between (a,b) and (a,c)
The verilog model is containing this specify
// Delays
(a=> b)= (0,0);
(a => c)= (0,0);
As you may know the real delay between (a,b) and (a,c) in SDF will replace (0,0) in the verilog model.
My question:
I do not want to use the delay (a,b) and (a,c)
I have internal signals called e,f for , and I want to use a delay (e,b) and (f,c)
with delay (a,b)=(e,b) and (a,c)=(f,c).
So, what can I add to my verilog model to make delays (a,b)=(e,b) and (a,c)=(f,c).
I am beginner,
thank you