Verilog-A. Is it possible?

[AMSA84]

Hi guys,

can someone tell me if it is possible to model a feedback loop for a dc-dc converter using verilog A? I am using cadence 6.

I'd like to model the resistive network (that will sample the output voltage), a comparator, a fixed voltage supple (reference), a sawtooth generator and a Flipflop D.

Regards.

 

[dick_freebird]

I believe it is possible, although I've never done it. My
veriloga skills extend to stealing other peoples' code and
making minor edits.

I'd be inclined to go at it in a hybrid approach - start with
the schematic and a working simulation, then replace
elements one by one with supplemental veriloga views.
You can make a config view and use hierarchy manager
to toggle between schematic detail and veriloga abstraction
in as fine-grained a way as your design structure supports.

You can doubtless find code-blocks for comparator,
voltage reference, DFF, probably even a ramp generator.
Doing them one at a time makes debug a whole lot easier.

 

[AMSA84]

Hi freebird,

Okay. I will investigate it.

By the way, tell me one thing, not related to the topic:

How can I get the input and output capacitances from the MOSFET that will be working as a high power mosfet? Is to design the gate driver. More, how can I estimate the Kn, Kp, Vthn, Vthp and Cox from simulation?

I've been told that I can save/print the values through the simulator. But those values are reliable? Going for the print?

Another thing that confuses me is that those values are not linear taking into account the W and L of the transistor. So, if I estimate those values, for example, Kn and Cox to get an optimum width for the transistor, the parameter obtained had to be obtained with a certain transistor that has a certain W and L. So if I am doing this for a certain W and L those values are for that particular W and L and I want to estimate and optimum W using a Kn and a Cox value that was obtained for a particular W and L? So, there is something here that doesn't match!

I don't know if I made myself clear.

Kind regards and thanks in advance.

 

[kemiyun]

Hey, I'm doing exactly this thing for switched capacitor DC-DC converter. And I can tell you it's not only possible, it is probably the best way to begin your simulations. Most of the parts you require are already in the ahdlLib, you can just modify them, although I don't think sawtooth generator is available. But nevertheless it should be easy to write, if you start writing it I will gladly help debugging it.

I think in another thread I've answered your second and third question. Unfortunately I didn't understand your fourth one.

 

[AMSA84]

Hi kemi,

Thanks for the reply. I've already answered to the other thread.

Regarding the Verilog-A, I've checked and I have some of those blocks that I want - for example a comparator. Those blocks in the ahdLib, are already programmed - that is, for example, in the case of the comparator, that symbol that we can put in our schematic has behind the code to implement it? Is that it? We just need to fill some of the stuffs that he has on the properties and that is. Is that right? But if the ahdLib didn't had that comparator I would need to code that comparator and then create the symbol.

I am correct? Just to have an idea.

 

[kemiyun]

Exactly, that's what ahdlLib is. I think eda tool companies are trying to promote use of ahdl so it's a plug and play kind of library and its codes are open (at least for cadence). And it includes mostly the examples from verilog-A reference manuals so you wouldn't have problems understanding them.

When you feel comfortable, move on writing your own blocks, starting with tweaking the existing models to your convenience.