verilog-a in synopsys custom design

[Yaso]

Dear All,

How can I use waveview for a schematic that contains only a veriloga symbol and a voltage source in hspice. No .tr0 file is created instead I'm having .valog!

Any help is really appreciated.

 

[vardan]

How can I use waveview for a schematic that contains only a veriloga symbol and a voltage source in hspice.

I understand that you netlist your design then simulate it with HSPICE (.tr0). To debug look into actual netlist that is simulated. Are there statements like .print. .probe. .plot? .tran?

When input files are correct, Verilog-A is handled properly

Regards,
Vardan

 

[Yaso]

I just checked it. Yes, I have written .tran in the .spi file and still I'n not getting .tr0 after simulating!

 

[vardan]

Yaso,
Synopsys has several analog simulators that support Verilog-A. As far as I know, only HSPICE creates *.tr0 files during transient simulation.
Do you use HSPICE?
Assume that you have a Verilog-A module, that is instantiated in SPICE deck. Substitute it with a dummy SPICE subcircuit. If simulation works, i.e you see anything changing in waveform viewer, then the problem is in your Verilog-A code.
It's not serious to debug your problems without seeing actual netlists and invocation commands.