May 16, 2013 #1 A Aforak Newbie level 5 Joined May 16, 2013 Messages 8 Helped 1 Reputation 2 Reaction score 1 Trophy points 1,283 Activity points 1,325 hi dudes, plz answer this whats the difference between <= and <+ in verilog A thank you
May 16, 2013 #2 D dave_59 Advanced Member level 3 Joined Dec 15, 2011 Messages 841 Helped 366 Reputation 736 Reaction score 360 Trophy points 1,353 Location Fremont, CA, USA Activity points 7,391 There is no <+ operator in Verilog
May 17, 2013 #3 A Aforak Newbie level 5 Joined May 16, 2013 Messages 8 Helped 1 Reputation 2 Reaction score 1 Trophy points 1,283 Activity points 1,325 dude! Iam asking about verilog-A, used for analog models
May 21, 2013 #4 imbichie Full Member level 6 Joined Jul 30, 2010 Messages 381 Helped 55 Reputation 110 Reaction score 54 Trophy points 1,308 Location Cochin/ Kerala/ India or Bangalore/ Karnataka/ Ind Activity points 3,580 Hi Aforak, From my understanding we must use the <+ when we are dealing with analog signals like V(out), I(in1, in2) etc. For driving these signals we need to use <+. But if the signal is not an analog then we can use the <=.
Hi Aforak, From my understanding we must use the <+ when we are dealing with analog signals like V(out), I(in1, in2) etc. For driving these signals we need to use <+. But if the signal is not an analog then we can use the <=.
May 27, 2013 #5 A Aforak Newbie level 5 Joined May 16, 2013 Messages 8 Helped 1 Reputation 2 Reaction score 1 Trophy points 1,283 Activity points 1,325 Yup got it shibin Thank you aforak